| 0 |
EXTIMER0 |
|
| 1 |
EXTIMER1 |
|
| 2 |
WDT |
|
| 3 |
|
|
| 4 |
|
|
| 5 |
|
|
| 6 |
|
|
| 7 |
|
|
| 8 |
|
|
| 9 |
UART_CA |
|
| 10 |
|
|
| 11 |
HDMI_NON_PCM |
|
| 12 |
SPDIF_IN_NON_PCM |
|
| 13 |
EMAC |
|
| 14 |
SE_DSP2UP |
|
| 15 |
TSP2AEON |
|
| 16 |
VIVALDI_STR |
|
| 17 |
VIVALDI_PTS |
|
| 18 |
DSP_MIU_PROT |
|
| 19 |
XIU_TIMEOUT |
|
| 20 |
DMDMCU2HK_INT |
|
| 21 |
VSYNC_VE4VBI |
VE “vsync” output |
| 22 |
FIELD_VE4VBI |
VE “field” output |
| 23 |
VDMCU2HK |
|
| 24 |
VE_DONE_TT |
VE teletext done interrupt |
| 25 |
INT_CCFL |
|
| 26 |
INT |
|
| 27 |
IR |
|
| 28 |
|
|
| 29 |
DEC_DSP2UP |
|
| 30 |
MIPS_WDT |
|
| 31 |
DSP2MIPS |
|
| 32 |
IR_INT_RC |
|
| 33 |
AU_DMA_BUF_INT |
|
| 34 |
VE_SW_WR2BUF |
|
| 35 |
UP_EMM_ECM |
|
| 36 |
8051_TO_MIPS_VPE0 |
INTR_CPUINT host0 int0 |
| 37 |
8051_TO_MIPS_VPE1 |
INTR_CPUINT host0 int1 |
| 38 |
8051_TO_AEON |
INTR_CPUINT host0 int2 |
| 39 |
|
|
| 40 |
AEON_TO_MIPS_VPE0 |
INTR_CPUINT host1 int0 |
| 41 |
AEON_TO_MIPS_VPE1 |
INTR_CPUINT host1 int1 |
| 42 |
AEON_TO_8051 |
INTR_CPUINT host1 int2 |
| 43 |
|
|
| 44 |
MIPS_VPE1_TO_MIPS_VPE0 |
INTR_CPUINT host2 int0 |
| 45 |
MIPS_VPE1_TO_AEON |
INTR_CPUINT host2 int1 |
| 46 |
MIPS_VPE1_TO_8051 |
INTR_CPUINT host2 int2 |
| 47 |
|
|
| 48 |
MIPS_VPE0_TO_MIPS_VPE1 |
INTR_CPUINT host3 int0 |
| 49 |
MIPS_VPE0_TO_AEON |
INTR_CPUINT host3 int1 |
| 50 |
MIPS_VPE0_TO_8051 |
INTR_CPUINT host3 int2 |
| 51 |
|
|
| 52 |
|
|
| 53 |
|
|
| 54 |
HDMITX_EDGE |
HDMITX’s edge triggered interrupts |
| 55 |
|
|
| 56 |
PVR2MI0 |
|
| 57 |
PVR2MI1 |
|
| 58 |
|
|
| 59 |
|
|
| 60 |
|
|
| 61 |
|
|
| 62 |
|
|
| 63 |
FRM_PM |
“FRoM PM”? Comes from PM intc’s FIQ part |