The first MCU/CPU that was ever used in MStar’s chips, as before that, you had to use an external MCU to control their display controller chips.
It’s also used in various in-chip subsystems like PM51, etc; and in various utlility chips like touchscreen controllers, DTV demodulators…
The OpenRISC architecture, or specifically, OpenRISC 1000 “or1k” core, although this does not imply that they didn’t made a compatible core themselves.
It is mostly seen used as a coprocessor in the system (the “AEON” coprocessor, and the “VPU”); it also lives in the TSP (MPEG-2 Transport Stream processor) block.
AEON R2 (or simply “R2”) is a custom 32-bit architecture that is heavily based off OpenRISC.
A family of MIPS CPU’s were used in MStar SoCs.
MIPS 74Kf
Used in all SigmaStar SoCs, many MStar SoCs, and basically chips made on this arch is the main scope of this project.